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december 2011 doc id 6104 rev 9 1/27 1 m41t56 serial real-time clock (rtc) with 56 bytes nvram features counters for seconds, minutes, hours, day, date, month, years, and century 32 khz crystal oscilla tor integrating load capacitance (12.5 pf) providing exceptional oscillator stability and high crystal series resistance operation serial interface supports i 2 c bus (100 khz protocol) ultra-low battery supply current of 450 na (typ at 3 v) 5 v 10% supply voltage timekeeping down to 2.5 v automatic power-fail detect and switch circuitry 56 bytes of general purpose ram software clock calibration to compensate crystal deviation due to temperature automatic leap year compensation operating temperature of ?40 c to 85 c available in an 8-lead, 150-mil, plastic soic (so8) rohs compliant ? lead-free second level interconnect 8 1 so8 150-mil width www.st.com
contents m41t56 2/27 doc id 6104 rev 9 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.3 stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.4 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.5 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
m41t56 list of tables doc id 6104 rev 9 3/27 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 9. power down/up mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 11. so8 ? 8-pin plastic small outline, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. carrier tape dimensions for so8 package (150-mil body width) . . . . . . . . . . . . . . . . . . . . 22 table 13. reel dimensions for 12 mm carrier tape - so8 package (150-mil body width). . . . . . . . . . 23 table 14. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 15. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
list of figures m41t56 4/27 doc id 6104 rev 9 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. 8-pin soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. m41t56 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. acknowledge sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 12. clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 13. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. power down/up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 15. so8 ? 8-pin plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 figure 16. carrier tape for so8 package (150-mil body width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 17. reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
m41t56 description doc id 6104 rev 9 5/27 1 description the m41t56 is a low-power, serial real-time clock (rtc) with 56 bytes of nvram. a built-in 32,768 hz oscillator (external crystal controlled) and the first 8 bytes of the ram are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. addresses and data are transferred serially via a two-line, bidirectional bus. the built-in address register is incremented automatically after each write or read data byte. the m41t56 clock has a built-in power sense circuit which detects power failures and automatically switches to the battery supply during power failures. the energy needed to sustain the ram and clock operations can be supplied from a small lithium coin cell. typical data retention time is in excess of 10 years with a 50 mah, 3 v lithium cell. the m41t56 is supplied in an 8-lead plastic soic package. figure 1. logic diagram ai02 3 04b o s ci v cc m41t56 v ss s cl o s co s da ft/out v bat
description m41t56 6/27 doc id 6104 rev 9 figure 2. 8-pin soic connections figure 3. m41t56 block diagram table 1. signal names osci oscillator input ocso oscillator output ft/out frequency test / output driver (open drain) sda serial data address input / output scl serial clock v bat battery supply voltage v cc supply voltage v ss ground 1 s da v ss s cl ft/out o s co o s ci v cc v bat ai02 3 06b m41t56 2 3 4 8 7 6 5 ai02566 s econd s o s cillator 3 2.76 8 khz voltage s en s e a nd s witch circuitry s erial bu s interface divider control logic addre ss regi s ter minute s century/hour s day date month year control ram (56 x 8 ) o s ci o s co ft/out v cc v ss v bat s cl s da 1 hz
m41t56 operation doc id 6104 rev 9 7/27 2 operation the m41t56 clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave address (d0h). the 64 bytes contained in the device can then be accessed sequentially in the following order: 1. seconds register 2. minutes register 3. century/hours register 4. day register 5. date register 6. month register 7. years register 8. control register 9. ram the clock continually monitors v cc for an out of tolerance condition. should v cc fall below v pfd , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to pr event erroneous da ta from being written to the device from an out of tolerance system. when v cc falls below v bat , the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. upon power-up, the device switches from battery to v cc at v bat and recognizes inputs when v cc goes above v pfd volts. 2.1 2-wire bus characteristics this bus is intended for communication between different ics. it consists of two lines: one bidirectional for data signals (sda) and one for clock signals (scl). both the sda and the scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock lin e is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: 2.1.1 bus not busy both data and clock lines remain high. 2.1.2 start data transfer a change in the state of the data line, from high to low, while the clock is high, defines the start condition.
operation m41t56 8/27 doc id 6104 rev 9 2.1.3 stop data transfer a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. 2.1.4 data valid the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start co ndition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition, a device that gives out a message is called ?transmitter,? the receiving device that gets the message is called ?receiver.? th e device that controls the message is called ?master.? the devices that are controlled by the master are called ?slaves.? 2.1.5 acknowledge each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case, the transmitter must leave the data line high to enable the master to generate the stop condition. figure 4. serial bus data transfer sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition
m41t56 operation doc id 6104 rev 9 9/27 figure 5. acknowledge sequence figure 6. bus timing requirements sequence ai00601 data output by receiver data output by transmitter sclk from master start clock pulse for acknowledgement 12 89 msb lsb ai005 8 9 s da p t s u: s to t s u: s ta thd: s ta s r s cl t s u:dat tf thd:dat tr thigh tlow thd: s ta tbuf s p
operation m41t56 10/27 doc id 6104 rev 9 2.2 read mode in this mode, the master reads the m41t56 slave after setting the slave address (see figure 7 on page 11 and figure 8 on page 11 ). following the write mode control bit (r/w = 0) and the acknowledge bit, the word address a n is written to the on-chip address pointer. next the start condition and slave address are repeated, followed by the read mode control bit (r/w = 1). at this point, the master transmitter becomes the master receiver. the data byte which was addressed w ill be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledg e bit. the m41t56 slave transm itter will now place the data byte at address a n + 1 on the bus. the master receiver reads and acknowledges the new byte and the address pointer is incremented to a n + 2. this cycle of reading consecutive addresses will continue until the master receiver sends a st op condition to the slave transmitter. an alternate read mode may also be implemented, whereby the master reads the m41t56 slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer, see figure 9 on page 11 . table 2. ac characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 4.5 to 5.5 v (except where noted). min max unit f scl scl clock frequency 0 100 khz t low clock low period 4.7 s t high clock high period 4 s t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 4s t su:sta start condition setup time (only relevant for a repeated start condition) 4.7 s t su:dat data setup time 250 ns t hd:dat (2) 2. transmitter must internally provi de a hold time to bridge the undefined re gion (300 ns max.) of the falling edge of scl. data hold time 0 s t su:sto stop condition setup time 4.7 s t buf time the bus must be free before a new transmission can start 4.7 s
m41t56 operation doc id 6104 rev 9 11/27 figure 7. slave address location figure 8. read mode sequence figure 9. alternative read mode sequence ai00602 r/w s lave addre ss s ta rt a 01000 11 m s b l s b ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (n) slave address s start r/w slave address ack ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address
operation m41t56 12/27 doc id 6104 rev 9 2.3 write mode in this mode the master transmitter transmits to the m41t56 slave receiver. bus protocol is shown in figure 10 on page 12 . following the start condition and slave address, a logic '0' (r/w = 0) is placed on the bus and indicates to the addressed device that word address a n will follow and is to be written to the on-chip add ress pointer. th e data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the ram on the reception of an acknowledge clock. the m41t56 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte (see figure 7 on page 11 ). 2.4 data retention mode with valid v cc applied, the m41t56 can be accessed as described above with read or write cycles. should the suppl y voltage decay, the m41t56 will automatically deselect, write protecting itself when v cc falls between v pfd (max) and v pfd (min). this is accomplished by internally inhibiting access to the clock registers and sram. when v cc falls below the battery backup switchover voltage (v so ), power input is switched from the v cc pin to the battery and the clock registers and sram are maintained from the attached battery supply. all outputs become high impedance. on power up, when v cc returns to a nominal value, write protection continues for t rec . for a further more detailed review of battery lifetime calculations, please see application note an1012. figure 10. write mode sequence ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (n) slave address
m41t56 clock operation doc id 6104 rev 9 13/27 3 clock operation the eight byte clock register (see ta bl e 3 ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. seconds, minutes, and hours are contained within the first three registers. bits d6 and d7 of clock register 2 (hours register) contain the century enable bit (ceb) and the ce ntury bit (cb). setting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. bits d0 through d2 of register 3 contain the day (day of week). registers 4, 5, and 6 contain the date (day of month), month, and years. the final register is the control register (this is described in the clock calibration section). bit d7 of register 0 contains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. when reset to a '0' the oscillator restarts within one second. the seven clock registers may be read one byte at a time, or in a sequential block. the control register (address location 7) may be accessed independently. provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. if a clock addr ess is being read, an update of the clock registers will be delayed by 250 ms to allow the read to be completed before the up date occurs. this will prevent a transition of data during the read. note: this 250 ms delay affects only the clock register update and does not alter the actual clock time. table 3. register map (1) 1. keys: s = sign bit ft = frequency test bit st = stop bit out = output level x = don't care ceb = century enable bit cb = century bit address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 0 st 10 seconds seconds seconds 00-59 1 x 10 minutes minutes minutes 00-59 2ceb (2) 2. when ceb is set to '1,' cb toggles from '0' to '1' or from '1' to '0' every 100 years (dependent upon the initial value set). when ceb is set to '0,' cb does not toggle. cb 10 hours hours century/hours 0-1/00-23 3xxxxx day day01-07 4 x x 10 date date date 01-31 5 x x x 10 m. month month 01-12 6 10 years years year 00-99 7 out ft s calibration control
clock operation m41t56 14/27 doc id 6104 rev 9 3.1 clock calibration the m41t56 is driven by a quartz-contro lled oscillator with a nominal frequency of 32,768 hz. the devices are te sted not to exceed 35 ppm (parts per million) oscillator frequency error at 25 c, which equates to about 1.53 minutes per month. with the calibration bits properly set, the accuracy of each m41t56 improves to better than 2 ppm at 25 c. the oscillation rate of any cryst al changes with temperature (see figure 11 on page 15 ). most clock chips compensate for crystal frequency and temperature shift error with cumbersome ?trim? capacitors. the m41t56 design, however, employs periodic counter correction. the calibration circuit adds or subt racts counts from the oscillator divider circuit at the divide by 256 stage, as shown in figure 11 on page 15 . the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration byte occupies the five lower order bits (d4-d0) in the control register (addr 7). this byte can be set to represent any value between 0 and 31 in binary form. bit d5 is the sign bit; '1' indicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only th e first 2 minutes in the 64 minu tes cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 ac tual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register. assu ming that the oscillator is in fact running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ? 2.75 minutes per month. two methods are available for ascertaining how much calibration a given m41t56 may require. the first involves simply setting the cl ock, letting it run for a month and comparing it to a known accurate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate hi s clock as his environment may require, even after the final product is packag ed in a non-user serviceable enclosure. all the designer has to do is provid e a simple utility that acce ssed the calibration byte. the second approach is better suited to a manufacturing environment, and involves the use of some test equipment. when the frequency test (ft) bit, the seventh-most significant bit in the control register, is set to a '1,' and the oscillator is runnin g at 32,768 hz, the ft/out pin of the device will toggle at 512 hz. any devi ation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.01024 hz wo uld indicate a +20 ppm oscillator frequency error, requiring a ?10(xx001010) to be loaded into the calibration byte for correction. note: setting or changing the calibration byte does not affect the frequency test output frequency.
m41t56 clock operation doc id 6104 rev 9 15/27 figure 11. crystal accuracy across temperature figure 12. clock calibration 3.2 output driver pin when the ft bit is not set, the ft/out pin becomes an output driver that reflects the contents of d7 of the control register. in other words, when d6 of location 7 is a '0' and d7 of location 7 is a '0' and then the ft/out pin will be driven low. note: the ft/out pin is open drain which requires an external pull-up resistor. 3.3 initial power-on defaults upon initial application of powe r to the device, the ft bit will be set to a '0' and the out bit will be set to a '1.' all other register bits will initially power-on in a random state. ai00999b ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 f = k x (t ?t o ) 2 k = ?0.036 ppm/ c 2 0.006 ppm/ c 2 t o = 25 c 5 c f ai00594b normal po s itive calibration negative calibration
maximum ratings m41t56 16/27 doc id 6104 rev 9 4 maximum ratings stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. caution: negative undershoots below ?0.3 v are not allowed on any pin while in the battery backup mode. table 4. absolute maximum ratings symbol parameter value unit t a ambient operating temperature ?40 to 85 c t stg storage temperature (v cc off, oscillator off) ?55 to 125 c t sld (1) 1. for so package, lead-free (pb-free) lead finish: reflow at peak tem perature of 260 c. the time above 255 c must not exceed 30 seconds. lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.3 to 7 v v cc supply voltage ?0.3 to 7 v i o output current 20 ma p d power dissipation 0.25 w
m41t56 dc and ac parameters doc id 6104 rev 9 17/27 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristics tables are derived from tests performed under the measurement conditions listed in ta bl e 5 : operating and ac measurement conditions . designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. figure 13. ac measurement i/o waveform table 5. operating and ac measurement conditions (1) 1. output hi-z is defined as the point where data is no longer driven. parameter value unit supply voltage (v cc ) 4.5 to 5.5 v ambient operating temperature (t a ) ?40 to 85 c load capacitance (c l ) 100 pf input rise and fall times 5ns input pulse voltages 0 to 3 v input and output timing ref. voltages 1.5 v table 6. capacitance symbol parameter (1)(2) 1. effective capacitance measur ed with power supply at 5v; sampled, not 100% tested. 2. at 25 c, f = 1 mhz. min max unit c in input capacitance (scl) 7 pf c out (3) 3. outputs deselected. output capacitance (sda, ft/out) 10 pf t lp low-pass filter input time c onstant (sda and scl) 0.25 1 s ai0256 8 0. 8 v cc 0.2v cc 0.7v cc 0. 3 v cc
dc and ac parameters m41t56 18/27 doc id 6104 rev 9 figure 14. power down/up mode ac waveforms table 7. dc characteristics symbol parameter test condition (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 4.5 to 5.5 v (except where noted). min typ max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current switch frequency = 100 khz 300 a i cc2 supply current (standby) scl, sda = v cc ? 0.3 v 100 a v il input low voltage ?0.3 1.5 v v ih input high voltage 3 v cc + 0.8 v v ol output low voltage i ol = 5ma, v cc = 4.5 v 0.4 v v bat (2) 2. stmicroelectronics recommends the rayovac br1225 or br1632 (or equivalent) as the battery supply. battery supply voltage 2.5 3 3.5 v i bat battery supply current t a = 25 c, v cc = 0 v, oscillator on, v bat = 3 v 450 550 na table 8. crystal electrical characteristics symbol parameter (1)(2) 1. these values are externally supplied for the so 8 package. stmicroelectronics recommends the kds dt- 38: 1ta/1tc252e127, tuning fork type (thru-hole) or the dmx-26s: 1tjs125fh2a212, (smd) quartz crystal for industrial tem perature operations. for contact info rmation on this crystal type, see section 8: references on page 25 . 2. load capacitors are integrated within the m41t56. circ uit board layout considerat ions for the 32.768 khz crystal of minimum trace lengths and isolation from rf generating signal s should be taken into account. min typ max unit f o resonant frequency 32.768 khz r s series resistance 60 k c l load capacitance 12.5 pf ai00595 v cc t fb t rec t pd t rb v pfd v so data retention time sda scl i bat
m41t56 dc and ac parameters doc id 6104 rev 9 19/27 table 9. power down/up mode ac characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 4.5 to 5.5 v (except where noted). min max unit t pd scl and sda at v ih before power-down 0 ns t fb v pfd (min) to v ss v cc fall time 300 s t rb v ss to v pfd (min) v cc rise time 100 s t rec scl and sda at v ih after power-up 10 s table 10. power down/up trip points dc characteristics symbol parameter (1)(2) 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 4.5 to 5.5 v (except where noted). min typ max unit v pfd power-fail deselect voltage 1.2 v bat 1.25 v bat 1.285 v bat v v so battery back-up switchover voltage v bat v
package mechanical data m41t56 20/27 doc id 6104 rev 9 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
m41t56 package mechanical data doc id 6104 rev 9 21/27 figure 15. so8 ? 8-pin plastic small package outline 1. drawing is not to scale. 1. drawing is not to scale. table 11. so8 ? 8-pin plastic small outline, package mechanical data symbol millimetres inches typ min max typ min max a1.750.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e1.27? ?0.050? ? h 0.25 0.50 0.010 0.020 k 08 08 l 0.40 1.27 0.016 0.050 l1 1.04 0.041 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
package mechanical data m41t56 22/27 doc id 6104 rev 9 figure 16. carrier tape for so8 package (150-mil body width) t k 0 p 1 a 0 b 0 p 2 p 0 center line s of cavity w e f d top cover tape u s er direction of feed am0 3 07 3 v1 table 12. carrier tape dimensions for so8 package (150-mil body width) package w d e p 0 p 2 fa 0 b 0 k 0 p 1 tunit bulk qty so8 12.00 0.30 1.50 +0.10/ ?0.00 1.75 0.10 4.00 0.10 2.00 0.10 5.50 0.05 6.50 0.10 5.30 0.10 2.20 0.10 8.00 0.10 0.30 0.05 mm 2500
m41t56 package mechanical data doc id 6104 rev 9 23/27 figure 17. reel schematic note: the dimensions given in ta b l e 1 3 incorporate tolerances that cover all variations on critical parameters. a d b f u ll r a di us t a pe s lot in core for t a pe s t a rt 2.5mm min.width g me asu red at h ub c n 40mm min. acce ss hole at s lot loc a tion t am0492 8 v1 table 13. reel dimensions for 12 mm carrier tape - so8 package (150-mil body width) a (max) b (min) c d (min) n (min) g t (max) 330 mm (13-inch) 1.5 mm 13 mm 0.2 mm 20.2 mm 60 mm 12.4 mm + 2/?0 mm 18.4 mm
part numbering m41t56 24/27 doc id 6104 rev 9 7 part numbering table 14. ordering information scheme example: m41t 56 m 6 e device type m41t supply voltage and write protect voltage 56 = v cc = 4.5 to 5.5 v package m = so8 temperature range 6 = ?40 c to 85 c shipping method e = lead-free package (ecopack ? ), tubes (1) 1. not recommended for new design. contact local st sales office for availability. f = lead-free package (ecopack ? ), tape & reel
m41t56 references doc id 6104 rev 9 25/27 8 references the crystal component supplier kds as cited in table 8: crystal electrical characteristics on page 18 can be contacted at http://www.kds.info/index_en.htm
revision history m41t56 26/27 doc id 6104 rev 9 9 revision history table 15. document revision history date revision changes mar-1999 1.0 first issue 23-dec-1999 1.1 soh28 package added 21-mar-2000 1.2 series resist ance max value changed ( ta b l e 8 ) 30-nov-2000 1.3 added psdip8 package 25-jan-2001 1.4 corrected graphic, measur ements of psdip8 (figure 18, table 14) 16-feb-2001 2.0 reformatted, table added ( ta bl e 1 6 ). 06-apr-2001 2.1 add temp./voltage information to characteristics ( ta b l e 7 , ta b l e 2 ); correct series resistance ( ta bl e 8 ) 17-jul-2001 2.2 basic formatting changes 02-aug-2002 2.3 modify reflow time and temperature footnote ( ta bl e 4 ); modify crystal electrical characteristics table footnotes ( ta bl e 8 ); removed psdip8 package 07-nov-2002 2.4 correct figure name ( features on page 1 ) 15-jun-2004 3.0 reformatted; add lead-free informat ion; update characteristics ( figure 11 ; ta b l e 4 , ta bl e 1 4 ) 11-sep-2006 4 changed document to new template; amalgamated diagrams in features on page 1 ; amended footnotes in table 3: register map ; updated package mechanical data in section 6: package mechanical data ; small text changes for entire document, removed lead packages from ta b l e 1 4 , ecopack compliant 09-oct-2006 5 updated package mechanical data in figure 15: so8 ? 8-pin plastic small package outline . 10-apr-2007 6 updated package information references that only so8 available (cover page, section 1 , section 4 , ta b l e 4 , ta b l e 8 , and ta bl e 1 4 ). 06-nov-2007 7 added lead-free second level interconnect information to cover page and section 6: package mechanical data ; updated ta b l e 4 , footnote 1 in ta bl e 8 ; addition of section 8: references . 13-dec-2007 8 updated cover page and section 8: references . 06-dec-2011 9 updated footnote 1 of table 4: absolute maximum ratings ; updated ecopack ? text in section 6: package mechanical data ; added footnote 1 to table 14: ordering information scheme ; added figure 16 , 17 , ta b l e 1 2 , 13 ; updated title; minor textual updates.
m41t56 doc id 6104 rev 9 27/27 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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